Accelerating Analog AI R&D for Neuromorphic Computing Takes Intelligence
11 DEC 2020
While artificial intelligence (AI) algorithms can be embedded in digital vonNeumann ICs, excessive size and energy consumption represents a significant barrier to the widespread adoption of such neuromorphic AI chips both at the “edge” and in the “cloud”.
While artificial intelligence (AI) algorithms can be embedded in digital vonNeumann ICs, excessive size and energy consumption represents a significant barrier to the widespread adoption of such neuromorphic AI chips both at the “edge” and in the “cloud”. The U.S. Semiconductor Research Corporation (SRC) & Semiconductor Industry Association (SIA) recently published a decadal-plan that includes as one of five seismic shifts, “Fundamental breakthroughs in analog hardware are required to generate smarter world-machine interfaces that can sense, perceive and reason” (Figure 1).
Real neurons are elongated cells with multiple synapses connecting to other neurons, and individual neurons as well as loops-of-neurons encode learning and memory in brains. The encoding in AI is generally represented by some real scalar parameter such as resistance or capacitance. Digital AI requires a local circuit of read/write transistors plus memory storage nodes to simulate just one synapse, which leads to high energy consumption for an entire synaptic array. In contrast, Analog AI chips show promise for >1000 times lower energy consumption compared to the best digital AI chips, because a single analog memory cell can elegantly encode the scalar synaptic potential of an artificial neuron. An interconnected array of such artificial synapses allows for hyper-efficient neuromorphic circuits that can perform “compute in memory” tasks.
Analog AI is clearly the elegant hardware solution to the world’s needs for better sensing and responding devices. So why are all the commercial AI chips available today built using inefficient digital VonNeumann CMOS? Digital AI chips with high reliability can be made in HVM commercial IC fabs today, while analog AI chips are still in R&D labs after decades!
Analog and Digital NVM
The ongoing challenge is atomic-scale materials engineering of complex alloy stacks, and the need for more precise control over compositional variations in analog arrays. Commercial Non-Volatile Memory (NVM) ICs use changes in resistance to encode information, including:
- Ferroelectric Random Access Memory (FRAM)
- Resistance-change Random Access Memory (RRAM)
- Phase-Change Memory (PCM)
Intermolecular has worked with leading memory IDMs on R&D of digital NVM technologies including RRAM, PCM, and FRAM. Multi-component and doped variants of oxides, nitrides, and chalcogenides have been created using Physical Vapor Deposition (PVD) for cross-bar architectures and also using Atomic-Layer Deposition (ALD) for 3D circuits.
Each NVM cell type for different applications requires control of the composition and structure, such as Germanium Antimony Telluride (GeSbTe or “GST”) in different compositions and with dopants as the memristor for RRAM or the phase-change material for PCM. Inherent complexity increases when a ternary compound is doped with a fourth- and often a fifth-element.
Digital NVM such as 3D-NAND today store up to 4 bits/cell, requiring control over 16 resistance levels. Analog NVM cells storing scalars have more difficult targets for electrical control, which call for more tight distributions of physical parameters, and the corresponding need for more control over fabrication processes.
The material stack needed to form one analog AI cell includes an artificial synapse with buffer layers between electrodes, and often requires a “selector” diode to prevent sneak leakage paths within arrays. If we consider that every layer in the stack is a multi-element compound, and the synapse and selector each likely require four to five elements in precise ratios, the number of possible combinations creates a daunting set of experiments to undertake and then characterize. Each layer must be optimized, while the entire stack must be co-optimized!
Accelerating R&D cycles-of-learning to meet commercial time-to-market goals remains challenging for all semiconductor manufacturers, but is especially difficult when exploring analog AI. Being efficient with resources is critical when depositing a wide range of multi-element thin films, characterizing device structures by testing physical and electrical parameters, and then extracting dependencies within multi-dimensional property spaces. For example, if a certain range of compositions provides low-leakage but tends toward poor thermal stability then that dependency must be quantified.
To characterize analog AI we need special synapse-like test-vehicles, so that certain current pulse “spikes” can be sent across the artificial synapses in the array. Properly timed spike sequences quantify the viability of the circuit to learn, as well as other target circuit properties.
The number of parameters that must be co-optimized really requires a fresh approach to overcome multi-element trade-offs (Figure 2). The left-side shows an abstract parameter space with a small target square near the edge of experimental data, while the right-side shows how machine learning (ML) could predict the best trade-off line within the target space. The prediction is based on atomic descriptors such as bond-energy and covalence, as well as on data from additional target properties. These ML methods have been applied to chalcogenide selector R&D.
For over 15 years we have helped customers find solutions for their development needs while reducing the risks that are associated with bringing in new materials and processes. By leveraging a proprietary High-Throughput Experimentation Platform to accelerate R&D, Intermolecular Services can increase the speed, quality, depth and breadth of materials understanding. Now part of the Performance Materials business of Merck KGaA Darmstadt, Germany, Intermolecular continues to offer a wide range of services with varying levels of processing, characterization, and analysis to address our customer’s material innovation challenges.